1. Field of the Invention
This invention concerns a semiconductor integrated circuit comprised of macrocells prepared in advance, such as gate arrays.
2. Description of Related Art
LSI manufacturing processes are divided into bulk processes, in which transistors, resistances and other elements are formed at prescribed positions on silicon substrate, and wiring processes, in which elements are connected by metal wiring to form circuit functions. In a gate array, the above-mentioned bulk processes are used to form in advance a bulk chip on which are regularly arranged basic cells (also called unit cells) in an array, so that, simply by changing the wiring processes, various logic circuits can be formed.
FIG. 34 shows a bulk chip used to form the input/output circuit of a semiconductor integrated circuit. As shown in FIG. 34, in the case of an ordinary gate array, the input/output circuit (hereafter abbreviated to “I/O circuit”) 10 of a semiconductor integrated circuit comprises main driver units 12a and 12b, and a predriver unit 14. In one of the main driver units 12a, a plurality of P-channel MOS (hereafter “PMOS”) transistors are arranged, and in the other main driver unit 12b, a plurality of N-channel MOS (hereafter “NMOS”) transistors are arranged. In the predriver unit 14 are arranged, in an array, a plurality of basic cells, comprising two PMOS and two NMOS transistors. The dimensions (gate width and gate length) of the transistors comprised by the predriver unit 14 are small compared with the dimensions of the transistors comprised by the main driver units 12a and 12b. 
FIG. 35 is a mask pattern diagram for a basic cell comprised of conventional semiconductor integrated circuits. As shown in FIG. 35, basic cells comprised by the predriver unit 14 comprise PMOS transistors Tr1, Tr2 and NMOS transistors Tr3, Tr4.
Each transistor is formed on a P-type Si substrate, not shown. PMOS transistors Tr1 and Tr2 are formed within an N-well 16 embedded in this substrate. Within this N-well 16, a P-type semiconductor region 18 is formed, and within this P-type semiconductor region 18, the active regions 20 of the PMOS transistors Tr1, Tr2 are formed. On top of these active regions 20 are provided two parallel polysilicon film stripes, as the gates G1, G2 of the PMOS transistors Tr1, Tr2, respectively.
In a region adjacent to this N-well, the active regions 22 of NMOS transistors Tr3, Tr4 are formed. On top of these active regions 22 are provided two parallel polysilicon film stripes, as the gates G3, G4 of the NMOS transistors Tr3, Tr4, respectively.
In this way, the PMOS transistor Tr2 and PMOS transistor Tr1 are juxtaposed, and the NMOS transistor Tr4 and NMOS transistor Tr3 are juxtaposed. The gates of these transistors Tr1 through Tr4 are mutually parallel. And, the gate G1 of PMOS transistor Tr1 and the gate G3 of NMOS transistor Tr3 are provided, that is, arranged in a straight line. Similarly, the gate G2 of PMOS transistor Tr2 and the gate G4 of NMOS transistor Tr4 are provided in a line.
The gate width W1 of gate G1 of PMOS transistor Tr1, the gate width W2 of gate G2 of PMOS transistor Tr2, the gate width W3 of gate G3 of NMOS transistor Tr3, and the gate width W4 of gate G4 of NMOS transistor Tr4, are all equal, with W1:W2:W3:W4=1:1:1:1.
Further, an active region 24 for power supply (VDD) connection is formed adjacent to PMOS transistor Tr2 within the N-well 16. Also, a P-type semiconductor region 26 is formed adjacent to NMOS transistor Tr4 outside the N-well 16, and in this P-type semiconductor region 26 is formed an active region 28 for a ground (GND) connection.
At both ends of each gate G1 through G4 are provided polysilicon films 30 for wiring connections. Each of these polysilicon films 30 is provided in a state of connection with the gates G1 through G4.
FIG. 36 shows an example of the above-mentioned I/O circuit. In the input buffer shown in FIG. 36A, an ESD protection circuit 32 and inverters 34, 36 are connected between the input signal terminal A and the output signal terminal Y. The ESD protection circuit 32 comprises a main driver unit; the inverters 34 and 36 comprise a predriver unit.
In the output buffer shown in FIG. 36B, transistors Tr1, Tr2 and inverters 34, 36 are connected between the input signal terminal A and output signal terminal Y. The transistors Tr1, Tr2 are comprised by the main driver unit, and the inverters 34, 36 are comprised by the predriver unit.
In the output buffer shown in FIG. 36C, transistors Tr1, Tr2, a two-input NAND circuit (hereafter “2NAND circuit”) 38, a two-input NOR circuit (hereafter “2NOR circuit”) 40, and an inverter 34 are connected between the input signal terminal A and enable signal terminal EB, and the output signal terminal Y. The transistors Tr1, Tr2 are comprised by the main driver unit, and the 2NAND circuit 38, 2NOR circuit 40, and inverter 34 are comprised by the predriver unit.
In this way, in the predriver unit inverters, 2NAND and 2NOR circuits are comprised by basic cells. In a gate array, the threshold voltage Vth and delay time Tpd of these circuits are adjusted through the number of transistors of fixed dimensions used to comprise the predriver unit. Next, an example of configuration of an inverter using basic cells is presented.
In FIG. 37 and FIG. 38, a first example of configuration of an inverter using basic cells is presented. FIG. 37 is a drawing of the inverter mask pattern. FIG. 38 shows a cross-section of the element structure formed by the mask pattern shown in FIG. 37. FIG. 38A is a cross-sectional diagram at the position of the line I-I in FIG. 37; FIG. 38B is a cross-sectional diagram at the position of the line J-J in FIG. 37. In FIG. 38, insulation layers provided between each layer are omitted.
As shown in FIGS. 38A and 38B, an N-well 16 is formed in the P-type Si substrate 72, and within this N-well 16 is formed a P-type semiconductor region 18. Within this P-type semiconductor region 18 are formed the active regions 20 of the PMOS transistors Tr1 and Tr2. On top of this active region 20 are provided gates G1, G2 of the PMOS transistors Tr1, Tr2.
In FIG. 37, shading indicating the first and second metal layers denotes areas where the first metal layer and second metal layer overlap. Also in FIG. 37, shading indicating first and second through-holes denotes areas where a first through-hole and second through-hole overlap. Here a first through-hole is formed between the first metal layer and the second metal layer; a second through-hole is formed between the second metal layer and the third metal layer.
In this inverter, the gate G1 of PMOS transistor Tr1 and gate G2 of PMOS transistor Tr2 are connected to the first metal layer 44 via the contacts 42 provided on the polysilicon films used for wiring connections. These gates G1 and G2 are electrically connected by the first metal layer 44, and this first metal layer 44 is connected to the input terminal IN.
Further, the gate G1 of PMOS transistor Tr1 and gate G3 of NMOS transistor Tr3 are connected to the first metal layer 48 via the contacts 46 provided on the polysilicon films for wiring connections. These gates G1, G3 are electrically connected by the first metal layer 48.
As shown in FIG. 38A, the active region 20 between the gate G1 of PMOS transistor Tr1 and gate G2 of PMOS transistor Tr2 is connected to the third metal layer 52 via the first and second through-holes 50. This third metal layer 52 is connected to the active region 24 used for connection to the power supply (VDD).
The other active regions 20 of the PMOS transistors Tr1, Tr2 are connected to the first metal layer 58 via respective contacts 56. As shown in FIG. 38B, the first metal layer 58 on top of these active regions 20 is connected by the second metal layer 62 on top of the gates G1 and G2, connected via the second through-holes 60. The first metal layer 58 is connected to the output terminal OUT.
The active region 22 between the gate G3 of the NMOS transistor Tr3 and the gate G4 of the NMOS transistor Tr4 is connected to the third metal layer 66 via the first and second through-holes 64. The third metal layer 66 is connected to the active region 28 used for connection to ground (GND). Further, the other active region 22 of the NMOS transistor Tr3 is connected to the first metal layer 70 via the contact 68. This first metal layer 70 is connected to the output terminal OUT.
FIG. 39 is a circuit diagram showing the connections of the inverter shown in FIG. 37. As shown in FIG. 39, the channel of the PMOS transistor Tr1 and the channel of the NMOS transistor Tr3 are connected in series between the power supply VDD and ground GND. Further, the channel of the PMOS transistor Tr2 and the channel of the NMOS transistor Tr3 are connected in series between the power supply VDD and ground GND. The gates of transistors Tr1 through Tr3 are each connected to the input terminal IN. The point of connection of the channels of the PMOS transistor Tr1 and the of NMOS transistor Tr3, and the point of connection of the channels of the PMOS transistor Tr2 and of the NMOS transistor Tr3, are both connected to the output terminal OUT.
Next, FIG. 40 shows a second example of configuration of an inverter using basic cells. FIG. 40 shows a mask pattern for the inverter. The various shadings in FIG. 40 each have the same meaning as in FIG. 37.
This inverter comprises two basic cells. The wiring of one of the basic cells is similar to that shown in FIG. 37. The wiring of the PMOS transistors Tr5 and Tr6 comprised by the other basic cell is similar to the wiring of the PMOS transistors Tr1 and Tr2 shown in FIG. 37. The gates G5 and G6 of the PMOS transistors Tr5, Tr6 are connected to the input terminal IN via the first metal layer 44. The active region 20 between the gates of the PMOS transistors Tr5 and Tr6 is connected to the power supply VDD via the first and second through-holes 50, and the other active regions 20 are connected to the output terminal OUT via the second metal layer 62.
FIG. 41 is a circuit diagram showing the connections of the inverter shown in FIG. 40. As shown in FIG. 41, each of the channels of the PMOS transistors Tr1, Tr2, Tr5 and Tr6 is connected in parallel between the power supply VDD and ground GND. Also, each of the channels of these PMOS transistors is connected in series with the channel of the NMOS transistor Tr3 between the power supply VDD and ground GND. The gates of each of transistors Tr1 through Tr6 are connected to the input terminal IN. The points of connection of the channels of each of the PMOS transistors with the channel of the NMOS transistor Tr3 are connected to the output terminal OUT.
However, in order to make the capacity of the PMOS and NMOS transistors equal, the gate width of PMOS gates must be made from double to quadruple the gate width of the NMOS transistor gate. Here “make the capacity of the PMOS and NMOS transistors equal” means that, for the example of an inverter, when the circuit threshold voltage Vth is set to ½ the power supply voltage, the channel currents for both the NMOS and PMOS transistors are the same. Hence, as shown in FIG. 37 and FIG. 40, the frequency of use of the NMOS transistor is low compared with the PMOS transistors, and so usage efficiency of elements within the basic cell is poor.
Further, in a conventional basic cell the gate length and gate width are fixed, so that fine adjustments to Vth and Tpd cannot be made. In particular, recently there have been increasingly frequent cases of special I/O cells developed using gate arrays; the inability to make fine adjustments to dimensions is a disadvantage.